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MCF5282 External Signals
these outputs act as the byte select signals that indicate valid data is to be latched or driven
onto a byte lane when driven low. For SRAM or Flash devices, the BS[3:0] outputs should
be connected to individual byte strobe signals. For SDRAM devices, the BS[3:0] should be
connected to individual SDRAM DQM signals. Note that most SDRAMs associate DQM3
with the MSB, in which case BS3 is connected to the SDRAM's DQM3 input.
These pins can also be configured as GPIO PJ[7:4].
14.2.1.4 Output Enable (OE)
This output signal indicates when an external device can drive data during external read
cycles.
This pin can also be configured as GPIO PE7.
14.2.1.5 Transfer Acknowledge (TA)
This signal indicates that the external data transfer is complete. During a read cycle, when
the processor recognizes TA, it latches the data and then terminates the bus cycle. During a
write cycle, when the processor recognizes TA, the bus cycle is terminated. If all bus cycles
support fast termination, TA can be tied low.
This pin can also be configured as GPIO PE6.
14.2.1.6 Transfer Error Acknowledge (TEA)
This signal indicates an error condition exists for the bus transfer. The bus cycle is
terminated and the CPU begins execution of the access error exception. This signal is an
input in master mode.
This pin can also be configured as GPIO PE5.
14.2.1.7 Read/Write (R/W)
This output signal indicates the direction of the data transfer on the bus. A logic 1 indicates
a read from a slave device and a logic 0 indicates a write to a slave device.
This pin can also be configured as GPIO PE4.
14.2.1.8 Transfer Size(SIZ[1:0])
When the device is in normal mode, static bus sizing lets the programmer change data bus
width between 8, 16, and 32 bits for each chip select. The SIZ[1:0] outputs specify the data
access size of the current external bus reference as shown in Table 14-6.
MOTOROLA
Chapter 14. Signal Descriptions
14-19
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