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Programmer's Model
Table 25-8. CANMCR Field Descriptions (continued)
Bits
Name
Supervisor/user data space. The SUPV bit places the FlexCAN registers in either supervisor or
user data space.
7
SUPV
0 Registers with access controlled by the SUPV bit are accessible in either user or supervisor
privilege mode.
1 Registers with access controlled by the SUPV bit are restricted to supervisor mode.
Self wake enable. This bit allows the FlexCAN to wake up when bus activity is detected after the
STOP bit is set. If this bit is set when the FlexCAN enters low-power stop mode, the FlexCAN will
monitor the bus for a recessive to dominant transition. If a recessive to dominant transition is
detected, the FlexCAN immediately clears the STOP bit and restarts its clocks.
If a write to CANMCR with SELFWAKE set occurs at the same time a recessive-to-dominant edge
SELF-
6
appears on the CAN bus, the bit will not be set, and the module clocks will not stop. The user
WAKE
should verify that this bit has been set by reading CANMCR. Refer to Section 25.4.11.2,
"Low-Power Stop Mode for Power Saving" for more information on entry into and exit from
low-power stop mode.
0 Self wake disabled.
1 Self wake enabled.
Auto-power save. The APS bit allows the FlexCAN to automatically shut off its clocks to save
power when it has no process to execute, and to automatically restart these clocks when it has a
5
APS
task to execute without any CPU intervention.
0 Auto-power save mode disabled; clocks run normally.
1 Auto-power save mode enabled; clocks stop and restart as needed.
Stop acknowledge. When the FlexCAN is placed in low-power stop mode and shuts down its
clocks, it sets the STOPACK bit. This bit should be polled to determine if the FlexCAN has entered
low-power stop mode. When the FlexCAN exits low-power stop mode, the STOPACK bit is cleared
4
STOPACK
once the FlexCAN's clocks are running.
0 The FlexCAN is not in low-power stop mode and its clocks are running.
1 The FlexCAN has entered low-power stop mode and its clocks are stopped
3–0
—
Reserved, should be cleared.
25.5.2 FlexCAN Control Register 0 (CANCTRL0)
7
Field BOFFMSK
Reset
R/W
Address
Figure 25-7. FlexCAN Control Register 0 (CANCTRL0)
Table 25-9 describes the CANCTRL0 fields.
25-22
6
5
ERRMSK
MCF5282 User's Manual
Description
4
3
—
RXMODE
0000_0000
R/W
IPSBAR + 0x1C_0006
2
1
0
TXMODE
MOTOROLA
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