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SDRAM Controller Operation
request flag. This refresh cycle includes a delay from any precharge to the auto-refresh
command, the auto-refresh command, and then a delay until any
allowed. Any SDRAM access initiated during the auto-refresh cycle is delayed until the
cycle is completed.
Figure 15-8 shows the auto-refresh timing. In this case, there is an SDRAM access when
the refresh request becomes active. The request is delayed by the precharge to
programmed into the active SDRAM bank by the CAS bits. The
generated and the delay required by DCR[RTIM] is inserted before the next
command is generated. In this example, the next bus cycle is initiated, but does not generate
an SDRAM access until T
command, it is passed to both blocks of external SDRAM.
CLKOUT
A[31:0]
SRAS
SCAS
DRAMW
SDRAM_CS[0] or [1]
15.2.3.6 Self-Refresh Operation
Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at
the same time to perform an internal refresh operation and to maintain the integrity of the
data stored in the SDRAM. The DRAM controller supports self-refresh with DCR[IS].
When IS is set, the
SELF
command is sent to the DRAM controller. Figure 15-9 shows the self-refresh operation.
15-16
is finished. Because both chip selects are active during the
RC
t
= 2
RCD
PALL
REF
Figure 15-8. Auto-Refresh Operation
command is sent to the SDRAM. When IS is cleared, the
MCF5282 User's Manual
command is
ACTV
ACTV
command is then
REF
t
= 6
RC
MOTOROLA
delay
ACTV
REF
ACTV
SELFX
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