Table of Contents
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bank select (SDRAM_CS1–0), 14-21
clock enable (SCKE), 14-21
column address strobe (SCAS), 14-21
row address strobe (SRAS), 14-21
summary, 15-4
write enable (DRAMW), 14-21
single-chip mode, 14-17
TEST, 14-32
UART modules
clear-to-send (UCTS1–0), 14-27
receive serial data input (URXD2–0), 14-27
request-to-send (URTS1–0), 14-27
transmit serial data output (UTXD2–0), 14-26
SRAM
cache, interaction, 4-3
features, 5-1
initialization, 5-3
operation
low-power modes, 7-7
overview, 5-1
power management, 5-4
programming model, 5-1
timing diagrams
bus cycle terminated by TA, 33-14
bus cycle terminated by TEA, 33-15
Stack pointer registers
BDM accesses, 29-33
overview, 2-3
supervisor, 2-7
user, 2-7
Start-of-frame (SOF), 25-14
STOP instruction, 29-4, 29-17
Stop mode, 7-6
STRLDSR instruction, 2-32
STUFFERR, 25-29
Subroutine call, 2-3
Supervisor programming model, 2-5
System clock
generation, 9-11
modes, 9-10
T
TAP controller, 31-7
TEST_LEAKAGE, 31-10
Time quanta clock, 25-14
Time stamp, 25-6, 25-13
Timer overflow interrupt, 20-22
Timers
DMA, see DMA timers
general purpose, see general purpose timers
programmable interrupt, see programmable inter-
rupt timers
watchdog, see watchdog timer, 18-2
Timing diagrams
MOTOROLA
INDEX
debug
BDM serial port AC timing, 33-28
real-time trace AC timing, 33-28
Ethernet
MII async input signal, 33-22
general input timing requirements, 33-11
GPIO, 33-18
digital input, 26-25
digital output, 26-26
2
I
C
input/output timing, 33-20
JTAG
BKPT timing, 33-27
boundary scan, 33-26
test access port, 33-26
test clock input timing, 33-25
TRST timing, 33-26
QADC
bypass mode conversion timing, 27-36
conversion in external positive edge trigger
conversion in gated mode, continuous scan, 27-67
conversion in gated mode, single scan, 27-66
conversion timing, 27-36
QSPI timing, 33-24
reset controller
RSTI and configuration override timing, 33-19
SDRAM controller
read cycle, 33-16
write cycle, 33-17
SRAM
bus cycle terminated by TA, 33-14
bus cycle terminated by TEA, 33-15
Trace exception, 2-14
Transmit bit error (BITERR), 25-29
TRAP instruction, 2-15
TRAP instruction exception, 2-16
Truncation, 17-20
U
UART modules
block diagram, 23-1
clock select registers (UCSRn), 23-8
clock source
baud rates, 23-19
divider, 23-18
external, 23-20
command registers (UCRn), 23-9
FIFO stack, 23-23
initialization, 23-30
input port change (UIPCRn), 23-12
memory map, 23-3
operation
looping modes
MCF5282 User's Manual
mode, 27-65
Index-15
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