Synthesizer Status Register (Synsr) - Motorola ColdFire MCF5281 User Manual

Memory Map and Registers
Table 9-4. SYNCR Field Descriptions (continued)
Bit(s) Name
5 FWKUP
4 —
3–2 STPMD
1–0 —
9.6.2.2

Synthesizer Status Register (SYNSR)

The SYNSR is a read-only register that can be read at any time. Writing to the SYNSR has
no effect and terminates the cycle normally.
7
Field PLLMODE PLLSEL
Reset
R/W
Address
Note: 1. Reset state determined during reset configuration.
2. See the LOCKS and LOCK bit descriptions.
Figure 9-4. Synthesizer Status Register (SYNSR)
9-8
Fast wakeup determines when the system clocks are enabled during wakeup from
stop mode.
1 System clocks enabled on wakeup regardless of PLL lock status
0 System clocks enabled only when PLL is locked or operating normally
Note: When FWKUP = 0, if the PLL or oscillator is enabled and unintentionally lost in
stop mode, the PLL wakes up in self-clocked mode or reference clock mode
depending on the clock that was lost. In external clock mode, the FWKUP bit has no
effect on the wakeup sequence.
Reserved, should be cleared.
Control PLL and CLKOUT operation in stop mode. The following table illustrates
STPMD operation in stop mode.
STPMD[1:0]
System
Clocks
00 Disabled
01 Disabled
10 Disabled
11 Disabled
Reserved, should be cleared.
6 5
PLLREF
See note 1
IPSBAR + 0x0012_0002
MCF5282 User's Manual
Description
Operation During Stop Mode
PLL
Enabled
Enabled
Disabled Enabled
Disabled Disabled
4 3
LOCKS LOCK LOCS
See note 2
R
OSC CLKOUT
Enabled Enabled
Enabled Disabled
Disabled
Disabled
2 1 0
—
000
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