Qadc Control Register 1 (Qacr1); Qacr1 Field Descriptions - Motorola ColdFire MCF5281 User Manual

Register Descriptions

27.6.5.2 QADC Control Register 1 (QACR1)

QACR1 is the mode control register for queue 1. This register governs queue operating
mode and the use of completion and/or pause interrupts. Typically, these bits are written
once when the QADC is initialized and are not changed thereafter.
Stop mode resets this register.
15
Field CIE1
Reset
R/W:
7
Field
Reset
R/W:
Address
Bit(s) Name
15 CIE1
14 PIE1
13 SSE1
12–8 MQ1n
7–0 —
27-14
14 13
PIE1 SSE1 MQ112
IPSBAR + 0x19_000c, 0x19_000d
Figure 27-9. QADC Control Register 1 (QACR1)
Table 27-6. QACR1 Field Descriptions
Queue 1 completion interrupt enable. Enables an interrupt request upon completion of queue 1.
The interrupt request is initiated when the conversion is complete for the last CCW in queue 1.
1 Enable queue 1 completion interrupt.
0 Disable queue 1 completion interrupt.
Queue 1 pause interrupt enable. Enables an interrupt request when queue 1 enters the pause
state. The interrupt request is initiated when conversion is complete for a CCW that has the
pause bit set.
1 Enable the queue 1 pause interrupt.
0 Disable the queue 1 pause interrupt.
Queue 1 single-scan enable. Enables a single-scan of queue 1 after a trigger event occurs. SSE1
may be set during the same write cycle that sets the MQ1 bits for one of the single-scan queue
operating modes. The single-scan enable bit can be written to 1 or 0, but is always read as a 0,
unless the QADC is in test mode. The QADC clears SSE1 when the single-scan is complete.
1 Allow a trigger event to start queue 1 in a single-scan mode.
0 Trigger events are ignored for queue 1 single-scan modes.
Selects the operating mode for queue 1. Table 27-7 shows the bits in the MQ1 field which
enable different queue 1 operating modes.
Reserved, should be cleared.
MCF5282 User's Manual
12 11 10
MQ111 MQ110
0000_0000
R/W
—
0000_0000
R
Description
9 8
MQ19 MQ18
0
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