Motorola ColdFire MCF5281 User Manual page 19

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27.4.7 Dedicated Analog Supply Signals ................................................................ 27-7
27.4.8 Dedicated Digital I/O Port Supply Signal..................................................... 27-7
27.5 Memory Map .................................................................................................... 27-7
27.6 Register Descriptions ........................................................................................ 27-8
27.6.1 QADC Module Configuration Register (QADCMCR) ................................ 27-8
27.6.2 QADC Test Register (QADCTEST) ............................................................ 27-9
27.6.3 Port Data Registers (PORTQA and PORTQB) ............................................ 27-9
27.6.4 Port QA and QB Data Direction Register (DDRQA and DDRQB) ........... 27-10
27.6.5 Control Registers ........................................................................................ 27-11
27.6.6 Status Registers........................................................................................... 27-19
27.6.7 Conversion Command Word Table (CCW) ............................................... 27-26
27.6.8 Result Registers .......................................................................................... 27-29
27.7 Functional Description.................................................................................... 27-31
27.7.1 Result Coherency........................................................................................ 27-31
27.7.2 External Multiplexing ................................................................................. 27-31
27.7.3 Analog Subsystem ...................................................................................... 27-34
27.8 Digital Control Subsystem.............................................................................. 27-37
27.8.1 Queue Priority Timing Examples ............................................................... 27-38
27.8.2 Boundary Conditions .................................................................................. 27-49
27.8.3 Scan Modes................................................................................................. 27-50
27.8.4 Disabled Mode............................................................................................ 27-50
27.8.5 Reserved Mode ........................................................................................... 27-50
27.8.6 Single-Scan Modes ..................................................................................... 27-50
27.8.7 Continuous-Scan Modes ............................................................................. 27-54
27.8.8 QADC Clock (QCLK) Generation ............................................................. 27-57
27.8.9 Periodic/Interval Timer............................................................................... 27-58
27.8.10 Conversion Command Word Table ............................................................ 27-59
27.8.11 Result Word Table ...................................................................................... 27-62
27.9 Signal Connection Considerations.................................................................. 27-62
27.9.1 Analog Reference Signals........................................................................... 27-63
27.9.2 Analog Power Signals................................................................................. 27-63
27.9.3 Conversion Timing Schemes ...................................................................... 27-64
27.9.4 Analog Supply Filtering and Grounding .................................................... 27-67
27.9.5 Accommodating Positive/Negative Stress Conditions ............................... 27-69
27.9.6 Analog Input Considerations ...................................................................... 27-71
27.9.7 Analog Input Pins ....................................................................................... 27-73
27.10 Interrupts ......................................................................................................... 27-75
27.10.1 Interrupt Operation ..................................................................................... 27-75
27.10.2 Interrupt Sources......................................................................................... 27-76
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