Initialization Sequence; Ecr[Ether_En] De-Assertion Effect On Fec; User Initialization (Before Ecr[Ether_En]) - Motorola ColdFire MCF5281 User Manual

Functional Description

17.4.1 Initialization Sequence

This section describes which registers are reset due to hardware reset, which are reset by
the FEC RISC, and what locations the user must initialize prior to enabling the FEC.
17.4.1.1 Hardware Controlled Initialization
In the FEC, registers and control logic that generate interrupts are reset by hardware. A
hardware reset deasserts output signals and resets general configuration bits.
Other registers reset when the ECR[ETHER_EN] bit is cleared. ECR[ETHER_EN] is
deasserted by a hard reset or may be deasserted by software to halt operation. By
deasserting ECR[ETHER_EN], the configuration control registers such as the TCR and
RCR will not be reset, but the entire data path will be reset.
Table 17-1. ECR[ETHER_EN] De-Assertion Effect on FEC
Descriptor Controller block
17.4.2 User Initialization (Prior to Asserting ECR[ETHER_EN])
The user needs to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The
exact values will depend on the particular application. The sequence is not important.
Ethernet MAC registers requiring initialization are defined in Table 17-2.
Table 17-2. User Initialization (Before ECR[ETHER_EN])
17-6
Register/Machine
XMIT block
RECV block
DMA block
RDAR
TDAR
Description
Initialize EIMR
Clear EIR (write 0xFFFF_FFFF)
TFWR (optional)
IALR / IAUR
GAUR / GALR
PALR / PAUR (only needed for full duplex flow control)
OPD (only needed for full duplex flow control)
MCF5282 User's Manual
Reset Value
Transmission is aborted (bad CRC
appended)
Receive activity is aborted
All DMA activity is terminated
Cleared
Cleared
Halt operation
RCR
TCR
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