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Revision
Date of
Number
Release
MOTOROLA
Table iii. Revision History
Substantive Changes
Changed text in Step 1 to read "If f
PRDIV8 = 1; otherwise PRDIV8 = 0."
Changed equation in Step 2 to the following:
DIV[5:0] =
2 x 200kHz x (1 + (PRDIV8 x 7))
Changed equation in Step 3 to the following:
f
=
CLK
2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7))
Changed equations in example to reflect revisions above.
Changed text to read "So, for f
will set FCLK to 196.43 kHz which is a valid frequency for the timing of
program and erase functions."
Changed text to read "Consider the follwoing example for f
Added "Page erase verify" category.
Added "Page erase verify" category and description.
Added "Access error" row.
Moved information in Section 8.4.6, "DMA Request Control Register," to
Section 16.2, "DMA Request Control (DMAREQC)."
Changed offset for the copy of RAMBAR to "0x008."
Changed CWTIC to CWTIF.
Changed text to read "Setting MPARK[PRK_LAST] causes the arbitration
pointer to be parked on the highest priority master."
Changed "÷ MFD (2–9)" to "÷ MFD (4–18)."
Changed equation in "Normal PLL Clock Mode" row to the following:
RFD
× 2(MFD + 2)/2
f
= f
sys
ref
Eliminated Section 12.4.1.4, "Code Example."
In "Reset: CSCR0" row, changed "D7, D6, D5" to "—, D19, D18."
Replaced "SCKE" with "SCKE."
Changed text to read "The transmit FIFO uses addresses from the start of the
FIFO to the location four bytes before the address programmed into the
FRSR."
Added the following footnote: "The receive buffer pointer, which contains the
address of the associated data buffer, must always be evenly divisible by 16.
The buffer must reside in memory external to the FEC. This value is never
modified by the Ethernet controller."
Added the following footnote: "The transmit buffer pointer, which contains
the address of the associated data buffer, must always be evenly divisible by
4. The buffer must reside in memory external to the FEC. This value is never
modified by the Ethernet controller."
About This Book
÷ 2 is greater than 12.8 MHz,
SYS
f
SYS
f
SYS
= 66 MHz, writing 0x54 to CFMCLKD
SYS
Revision History
Section/Page
6.4.3.1/6-18
6.4.3.1/6-18
6.4.3.1/6-18
6.4.3.1/6-18
6.4.3.1/6-18
= 66 MHz."
6.4.3.1/6-18
SYS
Table 6-12/6-16
Table 6-13/6-20
Table 6-14/6-25
Chapter 8 and
16.2/16-3
Figure 8-2/8-5
Table 8-5/8-8
8.5.2.1/8-11
Figure 9-2/9-4
Table 9-7/9-11
Chapter 12
Figure 12-4/12-8
Table 14-1/14-3
17.5.4.20/17-42
Table 17-36/17-48
Table 17-37/17-50
liii
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