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Bits
Name
31–12
—
Reserved, should be cleared.
11–8
PAVx
Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past
MAC or MSAC instructions generated an overflow during product calculation or the 48-bit
accumulation. When a MAC or MSAC instruction is executed, the PAVx flag associated with the
destination accumulator is used to form the general overflow flag, MACSR[V]. Once set, each flag
remains set until V is cleared by a MOV.L , MACSR instruction or the accumulator is loaded
directly.
7–4
7
OMC
Overflow/saturation mode. Used to enable or disable saturation mode on overflow. If set, the
accumulator is set to the appropriate constant on any operation which overflows the accumulator.
Once saturated, the accumulator remains unaffected by any other MAC or MSAC instructions until
either the overflow bit is cleared or the accumulator is directly loaded.
6
S/U
Signed/unsigned operations.
In integer mode:
S/U determines whether operations performed are signed or unsigned. It also determines the
accumulator value during saturation, if enabled.
0 Signed numbers. On overflow, if OMC is enabled, an accumulator saturates to the most positive
(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on both the instruction
and the value of the product that overflowed.
1 Unsigned numbers. On overflow, if OMC is enabled, an accumulator saturates to the smallest
value (0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.
In fractional mode:
S/U controls rounding while storing an accumulator to a general-purpose register.
0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a
general-purpose register as a 32-bit value.
1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when it
is moved to a general-purpose register. See Section 3.4.1.1.1, "Rounding." The resulting 16-bit
value is stored in the lower word of the destination register. The upper word is zero-filled. The
accumulator value is not affected by this rounding procedure.
5
F/I
Fractional/integer mode Determines whether input operands are treated as fractions or integers.
0 Integers can be represented in either signed or unsigned notation, depending on the value of S/U.
1 Fractions are represented in signed, fixed-point, two's complement notation. Values range from
-1 to 1- 2
Representation."
4
R/T
Round/truncate mode. Controls the rounding procedure for MOV.L ACCx,Rx, or MSAC.L
instructions when operating in fractional mode.
0 Truncate. The product's lsbs are dropped before it is combined with the accumulator.
Additionally, when a store accumulator instruction is executed (MOV.L ACCx,Rx), the 8 lsbs of
the 48-bit accumulator logic are simply truncated.
1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the
nearest 40-bit value. If the low-order 24 bits equal 0x80_0000, the upper 40 bits are rounded to
the nearest even (lsb = 0) value.See Section 3.4.1.1.1, "Rounding." Additionally, when a store
accumulator instruction is executed (MOV.L ACCx,Rx), the lsbs of the 48-bit accumulator logic
are used to round the resulting 16- or 32-bit value. If MACSR[S/U] = 0 and MACSR[R/T] = 1,
the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] = 1, the
low-order 24 bits are used to round the resulting 16-bit fraction.
3–0
3
N
Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC,
and load operations; it is not affected by MULS and MULU instructions.
MOTOROLA
Table 3-1. MACSR Field Descriptions
Operational Mode Fields
-15
for 16-bit fractions and -1 to 1 - 2
Chapter 3. Enhanced Multiply-Accumulate Unit (EMAC)
Description
-31
for 32-bit fractions. See Section 3.5.2, "Data
Flags
Memory Map/Register Set
3-7
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