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23.4 UART Module Signal Definitions
Figure 23-16 shows both the external and internal signal groups.
System Clock
or
External Clock (DTIN)
Control
Address Bus
Interface
to CPU
To Interrupt
Controller
or DMA
Figure 23-16. UART Block Diagram Showing External and Internal Interface Signals
An internal interrupt request signal (IRQ) is provided to notify the interrupt controller of an
interrupt condition. The output is the logical NOR of unmasked UISRn bits. The interrupt
level of a UART module is programmed in the interrupt controller.
The interrupt level and priority is programmed in the interrupt controller
UART0, ICR14 for UART1, and ICR15 for UART2. See Section 10.3.6, "Interrupt Control
Register (ICRnx, (x = 1, 2,..., 63))."
Note that the UARTs can also be configured to automatically transfer data by using the
DMA rather than interrupting the core. When the FIFO has data on the receive path, a DMA
request can be issued. For more information on generating DMA requests, refer to
Section 23.5.6.1.2, "Setting up the UART to Request DMA Service," and Section 16.2,
"DMA Request Control (DMAREQC)."
Table 23-12 briefly describes the UART module signals.
The terms 'assertion' and 'negation' are used to avoid
confusion between active-low and active-high signals.
'Asserted' indicates that a signal is active, independent of the
voltage level; 'negated' indicates that a signal is inactive.
MOTOROLA
UART Module
Internal Bus
Internal
Control
Logic
Data
IRQ
NOTE
Chapter 23. UART Modules
UART Module Signal Definitions
Clock Source
Generator
URTS
Output Port
UCTS
Input Port
URXD
Four-Character
Receive Buffer
UTXD
Two-Character
Transmit Buffer
External
Interface
Signals
ICR13 for
—
23-17
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