Table of Contents
Advertisement
Programming Model
24.5 Programming Model
Table 24-1 lists the configuration registers used in the I
IPSBAR
Offset
2
0x300
I
C Address Register (I2ADR) [p. 24-6]
2
0x304
I
C Frequency Divider Register (I2FDR) [p. 24-7]
2
0x308
I
C Control Register (I2CR) [p. 24-8]
2
0x30C
I
C Status Register (I2SR) [p. 24-9]
2
0x310
I
C Data I/O Register (I2DR) [p. 24-10]
2
24.5.1 I
C Address Register (I2ADR)
The I2ADR holds the address the I
not the address sent on the bus during the address transfer.
Field
Reset
R/W
Address
Table 24-2 describes I2ADR fields.
Bits
Name
7–1
ADR
Slave address. Contains the specific slave address to be used by the I
mode for an address match on the bus.
0
—
Reserved, should be cleared.
24-6
2
Table 24-1. I
C Interface Memory Map
[31:24]
2
C responds to when addressed as a slave. Note that it is
7
2
Figure 24-5. I
C Address Register (I2ADR)
Table 24-2. I2ADR Field Descriptions
MCF5282 User's Manual
2
C interface.
[23:16]
ADR
0000_0000
R/W
IPSBAR + 0x300
Description
2
C module. Slave mode is the default I
[15:8]
[7:0]
Reserved
Reserved
Reserved
Reserved
Reserved
1
0
—
MOTOROLA
2
C
Advertisement
Table of Contents
