Pulse Accumulator Flag Register (Gptpaflg) - Motorola ColdFire MCF5281 User Manual

Memory Map and Registers
Table 20-18. GPTPACTL Field Descriptions (continued)
Bit(s) Name
4 PEDGE
3–2 CLK
1 PAOVI
0 PAI

20.5.16 Pulse Accumulator Flag Register (GPTPAFLG)

Field
Reset
R/W
Address
Figure 20-18. Pulse Accumulator Flag Register (GPTPAFLG)
20-14
Pulse accumulator edge. Selects falling or rising edges on the PAI pin to increment the
counter.
In event counter mode (PAMOD = 0):
1 Rising PAI edge increments counter
0 Falling PAI edge increments counter
In gated time accumulation mode (PAMOD = 1):
1 Low PAI input enables divide-by-64 clock to pulse accumulator and trailing rising
edge on PAI sets PAIF flag.
0 High PAI input enables divide-by-64 clock to pulse accumulator and trailing falling
edge on PAI sets PAIF flag.
Note: The timer prescaler generates the divide-by-64 clock. If the timer is not active,
there is no divide-by-64 clock.
To operate in gated time accumulation mode:
1. Apply logic 0 to RSTI pin.
2. Initialize registers for pulse accumulator mode test.
3. Apply appropriate level to PAI pin.
4. Enable GPT.
Select the GPT counter input clock. Changing the CLK bits causes an immediate
change in the GPT counter clock input.
00 GPT prescaler clock (When PAE = 0, the GPT prescaler clock is always the GPT
counter clock.)
01 PACLK
10 PACLK/256
11 PACLK/65536
Pulse accumulator overflow interrupt enable. Enables the PAOVF flag to generate
interrupt requests.
1 PAOVF interrupt requests enabled
0 PAOVF interrupt requests disabled
Pulse accumulator input interrupt enable. Enables the PAIF flag to generate interrupt
requests.
1 PAIF interrupt requests enabled
0 PAIF interrupt requests disabled
7
—
IPSBAR + 0x1A_0019, 0x1B_0019
MCF5282 User's Manual
Description
2
PAOVF
0000_0000
R/W
1 0
PAIF
MOTOROLA