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2.2.1.1
Data Registers (D0–D7)
Registers D0–D7 are used as data registers for bit (1-bit), byte (8-bit), word (16-bit) and
longword (32-bit) operations; they can also be used as index registers.
2.2.1.2
Address Registers (A0–A6)
These registers can be used as software stack pointers, index registers, or base address
registers; they can also be used for word and longword operations.
2.2.1.3
Stack Pointer (A7)
Certain ColdFire implementations, including the MCF5282, support two unique stack
pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP).
This support provides the required isolation between operating modes of the processor. The
SSP is described in Section 2.2.3.2, "Supervisor/User Stack Pointers (A7 and
OTHER_A7)."
A subroutine call saves the PC on the stack and the return restores it from the stack. Both
the PC and the SR are saved on the supervisor stack during the processing of exceptions
and interrupts. The return from exception (RTE) instruction restores the SR and PC values
from the supervisor stack.
2.2.1.4
Program Counter (PC)
The PC contains the address of the currently executing instruction. During instruction
execution and exception processing, the processor automatically increments the contents of
the PC or places a new value in the PC, as appropriate. For some addressing modes, the PC
is used as a base address for PC-relative operand addressing.
MOTOROLA
Chapter 2. ColdFire Core
Processor Register Description
2-3
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