Figure 33-6 shows an SDRAM write cycle.
CLKOUT
D1
A[23:0]
SRAS
1
SCAS
DRAMW
D[31:0]
SDRAM_CS[1:0]
BS[3:0]
33.9 General Purpose I/O Timing
NUM
G1
CLKOUT High to GPIO Output Valid
G2
CLKOUT High to GPIO Output Invalid
G3
GPIO Input Valid to CLKOUT High
G4
CLKOUT High to GPIO Input Invalid
MOTOROLA
0
1
2
3
D3
Row
D2
D7
D2
ACTV
NOP
1
DACR[CASL] = 2
Figure 33-6. SDRAM Write Cycle
Table 33-13. GPIO Timing
(V
= 2.7 to 3.6 V, V
DD
Characteristic
Chapter 33. Electrical Characteristics
4
5
6
7
8
D4
D4
WRITE
NOP
1, 2
= 0 V, V
= 5 V)
SS
DDH
Symbol
t
CHPOV
t
CHPOI
t
PVCH
t
CHPI
General Purpose I/O Timing
9
10
11
12
Column
D8
D4
D4
PALL
Min
Max
—
12
2
—
10
—
2
—
Unit
ns
ns
ns
ns
33-17