Sram Initialization Code; Power Management; Typical Rambar Setting Examples - Motorola ColdFire MCF5281 User Manual

SRAM Programming Model
The ColdFire processor or an external emulator using the debug module can perform these
initialization functions.
5.3.3

SRAM Initialization Code

The following code segment describes how to initialize the SRAM. The code sets the base
address of the SRAM at 0x20000000 and then initializes the SRAM to zeros.
RAMBASE EQU $20000000
RAMVALID EQU $00000001
move.l #RAMBASE+RAMVALID,D0
movec.l D0, RAMBAR
The following loop initializes the entire SRAM to zero
lea.l RAMBASE,A0
move.l #16384,D0
SRAM_INIT_LOOP:
clr.l (A0)+)
subq.l #1,D0
bne.b SRAM_INIT_LOOP
looping
5.3.4

Power Management

As noted previously, depending on the configuration defined by the RAMBAR, instruction
fetch and operand read accesses may be sent to the SRAM and cache simultaneously. If the
access is mapped to the SRAM module, it sources the read data and the unified cache access
is discarded. If the SRAM is used only for data operands, asserting the ASn bits associated
with instruction fetches can decrease power dissipation. Additionally, if the SRAM
contains only instructions, masking operand accesses can reduce power dissipation.
Table 5-2 shows some examples of typical RAMBAR settings.
5-4
Table 5-2. Typical RAMBAR Setting Examples
Data Contained in SRAM
Code Only
Data Only
Both Code And Data
MCF5282 User's Manual
;set this variable to $20000000
;load RAMBASE + valid bit into D0.
;load RAMBAR and enable SRAM
;load pointer to SRAM
;load loop counter into D0
;clear 4 bytes of SRAM
;decrement loop counter
;if done, then
RAMBAR[7:0]
0x2B
0x35
0x21
exit; else continue
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