Descriptor Group Upper Address Register (Gaur); Ialr Field Descriptions; Gaur Field Descriptions - Motorola ColdFire MCF5281 User Manual

Bits
31–0
17.5.4.16 Descriptor Group Upper Address (GAUR)
The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash
table used in the address recognition process for receive frames with a multicast address.
This register must be initialized by the user.
31
Field
Reset
R/W
15
Field
Reset
R/W
Address
Figure 17-19. Descriptor Group Upper Address Register (GAUR)
Bits
31–0
17.5.4.17 Descriptor Group Lower Address (GALR)
The GALR register is written by the user. This register contains the lower 32 bits of the
64-bit hash table used in the address recognition process for receive frames with a multicast
address. This register must be initialized by the user.
MOTOROLA
Table 17-27. IALR Field Descriptions
Name
IADDR2 The lower 32 bits of the 64-bit hash table used in the address
recognition process for receive frames with a unicast
address. Bit 31 of IADDR2 contains hash index bit 31. Bit 0
of IADDR2 contains hash index bit 0.
Uninitialized
Uninitialized
IPSBAR + 0x1120
Table 17-28. GAUR Field Descriptions
Name
GADDR1 The GADDR1 register contains the upper 32 bits of the 64-bit
hash table used in the address recognition process for
receive frames with a multicast address. Bit 31 of GADDR1
contains hash index bit 63. Bit 0 of GADDR1 contains hash
index bit 32.
Chapter 17. Fast Ethernet Controller (FEC)
Description
GADDR1
R/W
GADDR1
R/W
Description
Programming Model
16
0
17-39