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Table 21-2 describes the DTMRn fields.
Bits
Name
15–8
PS
Prescaler value. The prescaler is programmed to divide the clock input (system clock/(16 or 1) or clock on
DTINn) by values from 1 (PS = 0x00) to 256 (PS = 0xFF).
7–6
CE
Capture edge.
00 Disable capture event output
01 Capture on rising edge only
10 Capture on falling edge only
11 Capture on any edge
5
OM
Output mode.
0 Active-low pulse for one system clock cycle (15 ns at 66 MHz).
1 Toggle output.
4
ORRI Output reference request, interrupt enable. If ORRI is set when DTERn[REF] = 1, a DMA request or an interrupt
occurs, depending on the value of DTXMRn[DMAEN] (DMA request if =1, interrupt if =0).
0 Disable DMA request or interrupt for reference reached (does not affect DMA request or interrupt on capture
function).
1 Enable DMA request or interrupt upon reaching the reference value.
3
FRR
Free run/restart
0 Free run. Timer count continues to increment after reaching the reference value.
1 Restart. Timer count is reset immediately after reaching the reference value.
2–1
CLK
Input clock source for the timer
00 Stop count
01 System clock divided by 1
10 System clock divided by 16. Note that this clock source is not synchronized with the timer; thus successive
time-outs may vary slightly.
11 DTINn pin (falling edge)
0
RST
Reset timer. Performs a software timer reset similar to an external reset, although other register values can still
be written while RST = 0. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked
unless the timer is enabled.
0 Reset timer (software reset)
1 Enable timer
21.2.7 DMA Timer Extended Mode Registers (DTXMRn)
DTXMRs, shown in Figure 21-3, program DMA request and increment modes for the
timers.
Field
DMAEN
Reset
R/W
Address
IPSBAR + 0x402 (DTXMR0); + 0x442 (DTXMR1); + 0x482 (DTXMR2); + 0x4C2
MOTOROLA
Table 21-2. DTMRn Field Descriptions
7
6
Figure 21-3. DTXMRn Bit Definitions
Chapter 21. DMA Timers (DTIM0–DTIM3)
DMA Timer Programming Model
Description
—
0000_0000
R/W
(DTXMR3)
1
0
MODE16
21-5
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