Sram Initialization - Motorola ColdFire MCF5281 User Manual

Table 5-1. SRAM Base Address Register (continued)
Bits Name
9 SPV
8 WP
7–6 —
5–1 C/I, SC, SD,
UC, UD
0 V
5.3.2

SRAM Initialization

After a hardware reset, the contents of the SRAM module are undefined. The valid bit of
the RAMBAR is cleared, disabling the module. If the SRAM requires initialization with
instructions or data, the following steps should be performed:
1. Load the RAMBAR mapping the SRAM module to the desired location within the
address space.
2. Read the source data and write it to the SRAM. There are various instructions to
support this function, including memory-to-memory move instructions, or the
MOVEM opcode. The MOVEM instruction is optimized to generate line-sized
burst fetches on 0-modulo-16 addresses, so this opcode generally provides
maximum performance.
3. After the data has been loaded into the SRAM, it may be appropriate to load a
revised value into the RAMBAR with a new set of attributes. These attributes
consist of the write-protect and address space mask fields.
MOTOROLA
Secondary port valid. Allows access by DMA
0 DMA access to memory is disabled.
1 DMA access to memory is enabled.
NOTE: The BDE bit in the second RAMBAR register must also be set to allow dual port
access to the SRAM. For more information, see Section 8.4.2, "Memory Base Address
Register (RAMBAR)."
Write protect. Allows only read accesses to the SRAM. When this bit is set, any attempted
write access will generate an access error exception to the ColdFire processor core.
0 Allows read and write accesses to the SRAM module
1 Allows only read accesses to the SRAM module
Reserved, should be cleared.
Address space masks (ASn)
These five bit fields allow certain types of accesses to be "masked," or inhibited from
accessing the SRAM module. The address space mask bits are:
C/I = CPU space/interrupt acknowledge cycle mask
SC = Supervisor code address space mask
SD = Supervisor data address space mask
UC = User code address space mask
UD = User data address space mask
For each address space bit:
0 An access to the SRAM module can occur for this address space
1 Disable this address space from the SRAM module. If a reference using this address
space is made, it is inhibited from accessing the SRAM module, and is processed like
any other non-SRAM reference.
These bits are useful for power management as detailed in Section 5.3.4, "Power
Management."
Valid. A hardware reset clears this bit. When set, this bit enables the SRAM module;
otherwise, the module is disabled.
0 Contents of RAMBAR are not valid
1 Contents of RAMBAR are valid
Chapter 5. Static RAM (SRAM)
SRAM Programming Model
Description
5-3