Uart Baud Rate Generator Registers (Ubg1N/Ubg2N); Uisrn/Uimrn Field Descriptions - Motorola ColdFire MCF5281 User Manual

Register Descriptions
Table 23-9 describes UISRn and UIMRn fields.
Bits Name
7 COS Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt.
6–3 — Reserved, should be cleared.
2 DB Delta break.
0 No new break-change condition to report. Section 23.3.5, "UART Command Registers (UCRn),"
describes the
1 The receiver detected the beginning or end of a received break.
1 FFULL/ RxRDY (receiver ready) if UMR1n[FFULL/RxRDY] = 0; FIFO full (FFULL) if
RxRDY UMR1n[FFULL/RxRDY] = 1. Duplicate of USRn[FFULL/RxRDY]. If FFULL is enabled for UART0
or UART1, DMA channels 2 or 3 are respectively interrupted when the FIFO is full.
0 TxRDY Transmitter ready. This bit is the duplication of USRn[TxRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters
loaded into the transmitter holding register when TxRDY = 0 are not sent.
1 The transmitter holding register is empty and ready to be loaded with a character.

23.3.11 UART Baud Rate Generator Registers (UBG1n/UBG2n)

The UBG1n registers hold the MSB, and the UBG2n registers hold the LSB of the preload
value. UBG1n and UBG2n concatenate to provide a divider to the system clock for
transmitter/receiver operation, as described in Section 23.5.1.2.1, "System Clock Baud
Rates."
7
Field
Reset
R/W
Address
Figure 23-12. UART Baud Rate Generator Register (UBG1n)
7
Field
Reset
R/W
Address
Figure 23-13. UART Baud Rate Generator Register (UBG2n)
23-14
Table 23-9. UISRn/UIMRn Field Descriptions
-
RESET BREAK CHANGE INTERRUPT
IPSBAR + 0x218 (UBG10), 0x258 (UBG11), 0x298 (UBG12)
IPSBAR + 0x21C (UBG20), 0x25C (UBG21) 0x29C (UBG22)
MCF5282 User's Manual
Description
command.
Divider MSB
0000_0000
W
Divider LSB
0000_0000
W
0
0
MOTOROLA