Qadc Module Configuration Register (Qadcmcr); Register Descriptions; Qadc Memory Map - Motorola ColdFire MCF5281 User Manual

Register Descriptions

IPSBAR +
Offset
0x19_0000
0x19_0002
0x19_0004
0x19_0006
0x19_0008 Port QA Data Direction Register (DDRQA) Port QB Data Direction Register (DDRQB)
0x19_000a
0x19_000c
0x19_000e
0x19_0010
0x19_0012
0x19_0014–
0x19_01fe
0x19_0200–
0x19_027e
0x19_0280–
0x19_02fe
0x19_0300–
0x19_037e
0x19_0380–
0x19_03fe
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only
addresses have no effect and result in a cycle termination transfer error.
2
Access results in the module generating an access termination transfer error if not in test mode.
3
Read/writes have no effect and the access terminates with a transfer error exception.
27.6 Register Descriptions
This subsection describes the QADC registers.

27.6.1 QADC Module Configuration Register (QADCMCR)

The QADCMCR contains bits that control QADC debug and stop modes and determine the
privilege level required to access most registers.
15
Field QSTOP
Reset
R/W: R/W
27-8
Table 27-2. QADC Memory Map
MSB
QADC Module Configuration Register (QADCMCR)
QADC Test Register (QADCTEST)
Port QA Data Register (PORTQA)
QADC Control Register 0 (QACR0)
QADC Control Register 1 (QACR1)
QADC Control Register 2 (QACR2)
QADC Status Register 0 (QASR0)
QADC Status Register 1 (QASR1)
Conversion Command Word Table (CCW)
Right Justified, Unsigned Result Register (RJURR)
Left Justified, Signed Result Register (LJSRR)
Left Justified, Unsigned Result Register (LJURR)
14 13
QDBG
MCF5282 User's Manual
LSB
2
3
Reserved
Port QB Data Register (PORTQB)
(3)
Reserved
—
0000_0000
R
1
Access
S
S
—
S/U
S/U
S/U
S/U
S/U
S/U
S/U
—
S/U
S/U
S/U
S/U
8
MOTOROLA