Programmable Interrupt Timer Modules Memory Map; Memory Map And Registers - Motorola ColdFire MCF5281 User Manual

19.5 Memory Map and Registers

This subsection describes the memory map and register structure for PIT0–PIT3.
19.5.1 Memory Map
Refer to Table 19-2 for a description of the memory map.
This device has four programmable interrupt timers with the following IPSBAR offset for
base address locations for each timer.
PIT0: 0x0015_0000
PIT1: 0x0016_0000
PIT2: 0x0017_0000
PIT3: 0x0018_0000
Table 19-2. Programmable Interrupt Timer Modules Memory Map
IPSBAR Offset
for PITx
Address
0x001x_0000
0x001x_0002
0x001x_0004
0x001x_0006
1
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor
only addresses have no effect and result in a cycle termination transfer error.
2
Accesses to unimplemented address locations have no effect and result in a cycle termination transfer error.
19.5.2 Registers
The PIT programming model consists of these registers:
• The PIT control and status register (PCSR) configures the timer's operation.
• The PIT modulus register (PMR) determines the timer modulus reload value.
• The PIT count register (PCNTR) provides visibility to the counter value.
MOTOROLA Chapter 19. Programmable Interrupt Timer Modules (PIT0–PIT3)
Bits 15–8
PIT Control and Status Register (PCSR)
PIT Modulus Register (PMR)
PIT Count Register (PCNTR)
Unimplemented
Memory Map and Registers
Bits 7–0
2
1
Access
S
S
S/U
—
19-3