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DTMRn[CLK] selects the clock input source. A programmable prescaler divides the clock
input by values from 1 to 256. The prescaler output is an input to the 32-bit counter,
DTCNn.
21.2.2 Capture Mode
Each DMA timer has a 32-bit timer capture register (DTCRn) that latches the counter value
when the corresponding input capture edge detector senses a defined DTINn transition. The
capture edge bits (DTMRn[CE]) select the type of transition that triggers the capture and
sets the timer event register capture event bit, DTERn[CAP]. If DTERn[CAP] is set and
DTXMRn[DMAEN] is one, a DMA request is asserted. If DTERn[CAP] is set and
DTXMRn[DMAEN] is zero, an interrupt is asserted.
21.2.3 Reference Compare
Each DMA timer can be configured to count up to a reference value, at which point
DTERn[REF] is set. If DTMRn[ORRI] is one and DTXMRn[DMAEN] is zero, an interrupt
is asserted. If DTMRn[ORRI] is one and DTXMRn[DMAEN] is one, a DMA request is
asserted. If the free run/restart bit DTMRn[FRR] is set, a new count starts. If it is clear, the
timer keeps running.
21.2.4 Output Mode
When a timer reaches the reference value selected by DTRR, it can send an output signal
on DTOUTn. DTOUTn can be an active-low pulse or a toggle of the current output as
selected by the TMRn[OM] bit.
21.2.5 Memory Map
The timer module registers, shown in Table 21-1, can be modified at any time.
IPSBAR
[31:24]
Offset
DMA Timer0 Mode Register (DTMR0)
0x400
0x404
0x408
0x40C
DMA Timer1 Mode Register (DTMR1)
0x440
0x444
MOTOROLA
Table 21-1. DMA Timer Module Memory Map
[23:16]
DMA Timer0 Reference Register (DTRR0)
DMA Timer0 Capture Register (DTCR0)
DMA Timer0 Counter Register (DTCN0)
DMA Timer1 Reference Register (DTRR1)
Chapter 21. DMA Timers (DTIM0–DTIM3)
DMA Timer Programming Model
[15:8]
DMA Timer0 Extended
Mode Register (DTXMR0)
DMA Timer1 Extended
Mode Register (DTXMR1)
[7:0]
DMA Timer0 Event
Register (DTER0)
DMA Timer1 Event
Register (DTER1)
21-3
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