Status Registers - Motorola ColdFire MCF5281 User Manual

MQ2[12:8]
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

27.6.6 Status Registers

This subsection describes the QADC status registers.
27.6.6.1 QADC Status Register 0 (QASR0)
QASR0 contains information about the state of each queue and the current A/D conversion.
The bits in this register are read anytime. For flag bits (CF1, PF1, CF2, PF2, TOR1, TOR2),
writing a 1 has no effect; writing a 0 clears the bit. For QS[9:6] and CWP, writes have no
effect. Stop mode resets this register.
The end of a queue is identified in the following cases:
• When execution is complete on the CCW in the location prior to the one
pointed to by BQ2
MOTOROLA
Table 27-9. Queue 2 Operating Modes (continued)
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Reserved mode
Reserved mode
Software triggered continuous-scan mode
Externally triggered rising edge continuous-scan mode
Externally triggered falling edge continuous-scan mode
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Periodic timer continuous-scan mode: time = QCLK period x 2
Reserved mode
Chapter 27. Queued Analog-to-Digital Converter (QADC)
Operating Modes
14
15
16
17
Register Descriptions
7
8
9
10
11
12
13
14
15
16
17
27-19