Motorola ColdFire MCF5281 User Manual page 707

Command Sequence:
WCREG MS ADDR
??? 'NOT READY'
Operand Data:
Result Data:
29.5.3.3.11 Read Debug Module Register (
Read the selected debug module register and return the 32-bit result. The only valid register
selection for the
RDMREG
clears CSR[FOF, TRG, HALT, BKPT]; as well as the trigger status bits (CSR[BSTAT]) if
either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and
no level-2 breakpoint has been enabled.
Command/Result Formats:
15
Command 0x2
Result
Table 29-20 shows the definition of DRc encoding.
MOTOROLA
MS ADDR
'NOT READY'
Figure 29-36.
WCREG
This instruction requires two longword operands. The first selects
the register to which the operand data is to be written; the second
contains the data.
Successful write operations return 0xFFFF. Bus errors on the write
cycle are indicated by the setting of bit 16 in the status message and
by a data pattern of 0x0001.
command is CSR (DRc = 0x00). Note that this read of the CSR
12 11
0xD
Figure 29-37.
RDMREG
Chapter 29. Debug Support
Background Debug Mode (BDM)
MS DATA
'NOT READY'
WRITE
LS DATA
CONTROL
'NOT READY'
REGISTER
Command Sequence
)
RDMREG
8 7 5
100
D[31:16]
D[15:0]
Command/Result Formats
XXX
'NOT READY'
NEXT CMD
'CMD COMPLETE'
XXX
BERR
NEXT CMD
'NOT READY'
4 0
DRc
29-35