Set-And-Forget Timer Operation; Functional Description; Pit Modulus Register (Pmr); Pit Count Register (Pcntr) - Motorola ColdFire MCF5281 User Manual

Functional Description

15
Field PM15
Reset
R/W
7
Field PM7
Reset
R/W
Address IPSBAR + 0x0015_0002 and 0x0015_0003 (PIT0); 0x0016_0002 and 0x0016_0003 (PIT1); 0x0017_0002
and 0x0017_0003 (PIT2); 0x0018_0002 and 0x0018_0003 (PIT3)

19.5.2.3 PIT Count Register (PCNTR)

The 16-bit, read-only PCNTR contains the counter value. Reading the 16-bit counter with
two 8-bit reads is not guaranteed to be coherent. Writing to PCNTR has no effect, and write
cycles are terminated normally.
15
Field PC15
Reset
R/W
7
Field PC7
Reset
R/W
Address IPSBAR + 0x0015_0004 and 0x0015_0005 (PIT0), 0x0016_0004 and 0x0016_0005 (PIT1), 0x0017_0004
19.6 Functional Description
This subsection describes the PIT functional operation.

19.6.1 Set-and-Forget Timer Operation

This mode of operation is selected when the RLD bit in the PCSR register is set.
When the PIT counter reaches a count of 0x0000, the PIF flag is set in PCSR. The value in
the modulus register is loaded into the counter, and the counter begins decrementing toward
0x0000. If the PIE bit is set in PCSR, the PIF flag issues an interrupt request to the CPU.
19-6
14 13
PM14 PM13 PM12
6 5
PM6 PM5 PM4
Figure 19-3. PIT Modulus Register (PMR)
14 13
PC14 PC13 PC12
6 5
PC6 PC5 PC4
and 0x0017_0005 (PIT2), 0x0018_0004 and 0x0018_0005 (PIT3)
Figure 19-4. PIT Count Register (PCNTR)
MCF5282 User's Manual
12 11
PM11 PM10
1111_1111
R/W
4 3
PM3 PM2
1111_1111
R/W
12 11
PC11 PC10
1111_1111
R
4 3
PC3 PC2
1111_1111
R
10 9 8
PM9 PM8
2 1 0
PM1 PM0
10 9 8
PC9 PC8
2 1 0
PC1 PC0
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