Dma Module Features; Dma Signal Diagram - Motorola ColdFire MCF5281 User Manual

Overview
Internal
Bus
External
Requests
Data Path
Read Data Bus
Throughout this chapter "external request" and DREQ are used
to refer to a DMA request from one of the on-chip UARTS or
DMA timers. For details on the connections associated with
DMA request inputs, see Section 16.2, "DMA Request Control
(DMAREQC)."

16.1.1 DMA Module Features

The DMA controller module features are as follows:
• Four independently programmable DMA controller channels
• Auto-alignment feature for source or destination accesses
• Dual-address transfers
• Channel arbitration on transfer boundaries
• Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
• Continuous-mode or cycle-steal transfers
• Independent transfer widths for source and destination
• Independent source and destination address registers
16-2
Channel 0 Channel 1
SAR0 SAR1
DAR0 DAR1
BCR0 BCR1
DCR0 DCR1
DSR0 DSR1
Channel
Requests
Channel
Enables
MUX
Control
Data Path
Control
Write Data Bus
Figure 16-1. DMA Signal Diagram
NOTE
MCF5282 User's Manual
Channel 2 Channel 3
SAR2 SAR3
DAR2 DAR3
BCR2 BCR3
DCR2 DCR3
DSR2 DSR3
Channel
Attributes
System Bus Address
MUX
System Bus Size
Current Master Attributes
Arbitration/
Control
Interrupts
Bus Interface
Registered
Bus Signals
MOTOROLA