Table of Contents
Advertisement
Bits
Name
8
CPHA
Clock phase. Defines the QSPI_CLK clock-phase.
0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK.
1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.
7–0
BAUD
Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value of zero disables
the QSPI. A value of 1 is an invalid setting. The desired QSPI_CLK baud rate is related to the system clock
and QMR[BAUD] by the following expression:
QMR[BAUD] = f
Figure 22-4 shows an example of a QSPI clocking and data transfer.
QSPI_CLK
QSPI_Dout
15
msb
QSPI_Din
15
A
QSPI_CS
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
Figure 22-4. QSPI Clocking and Data Transfer Example
22.5.2 QSPI Delay Register (QDLYR)
Figure 22-5 shows the QDLYR.
15
14
Field SPE
Reset
R/W
Address
MOTOROLA
Chapter 22. Queued Serial Peripheral Interface (QSPI) Module
Table 22-4. QMR Field Descriptions (continued)
/ [2 × (desired QSPI_CLK baud rate)]
SYS
14
13
12
11
10
14
13
12
11
10
QCD
Figure 22-5. QSPI Delay Register (QDLYR)
Description
9
8
7
6
5
9
8
7
6
5
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
8
7
0000_0100_0000_0100
R/W
IPSBAR + 0x344
Programming Model
4
3
2
1
0
4
3
2
1
0
DTL
B
0
22-11
Advertisement
Table of Contents
