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1.1.4
Chip Select
Programmable chip select outputs provide a glueless connection to external memory and
peripheral circuits, providing all handshaking and timing signals for automatic wait-state
insertion and data bus sizing.
1.1.5
Power Management
The MCF5282 incorporates several low-power modes of operation which are entered under
program control and exited by several external trigger events. An integrated Power-On
Reset (POR) circuit monitors the input supply and forces an MCU reset as the supply
voltage rises. The Low Voltage Detect (LVD) section monitors the supply voltage and is
configurable to force a reset or interrupt condition if it falls below the LVD trip point. The
RAM standby switch provides power to RAM when the supply voltage is higher than the
standby voltage. If the supply voltage to chip falls below the standby battery voltage, the
RAM is switched over to the standby supply.
1.1.6
General Input/Output Ports
All of the pins associated with the external bus interface may be used for several different
functions. Their primary function is to provide an external memory interface to access
off-chip resources. When not used for this function, all of the pins may be used as
general-purpose digital I/O pins. In some cases, the pin function is set by the operating
mode, and the alternate pin functions are not supported.
The digital I/O pins on the MCF5282 are grouped into 8-bit ports. Some ports do not use
all eight bits. Each port has registers that configure, monitor, and control the port pins.
1.1.7
Interrupt Controllers (INTC0/INTC1)
There are two interrupt controllers on the MCF5282, each of which can support up to 63
interrupt sources for a total of 126. Each interrupt controller is organized as 7 levels with 9
interrupt sources per level. Each interrupt source has a unique interrupt vector, and 56 of
the 63 sources of a given controller provide a programmable level [1-7] and priority within
the level.
1.1.8
SDRAM Controller
The SDRAM controller provides all required signals for glueless interfacing to a variety of
JEDEC-compliant SDRAM devices. SRAS/SCAS address multiplexing is software
configurable for different page sizes. To maintain refresh capability without conflicting
with concurrent accesses on the address and data buses, SRAS, SCAS, DRAMW,
SDRAM_CS[1:0], and SCKE are dedicated SDRAM signals.
MOTOROLA
Chapter 1. Overview
MCF5282 Key Features
1-11
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