Descriptor Group Lower Address Register (Galr); Fifo Transmit Fifo Watermark Register (Tfwr); Galr Field Descriptions - Motorola ColdFire MCF5281 User Manual

Programming Model
31
Field
Reset
R/W
15
Field
Reset
R/W
Address
Figure 17-20. Descriptor Group Lower Address Register (GALR)
Bits
31–0

17.5.4.18 FIFO Transmit FIFO Watermark Register (TFWR)

The TFWR is a 2-bit read/write register programmed by the user to control the amount of
data required in the transmit FIFO before transmission of a frame can begin. This allows
the user to minimize transmit latency (TFWR = 0x) or allow for larger bus access latency
(TFWR = 11) due to contention for the system bus. Setting the watermark to a high value
will minimize the risk of transmit FIFO underrun due to contention for the system bus. The
byte counts associated with the TFWR field may need to be modified to match a given
system requirement (worst case bus access latency by the transmit data DMA channel).
31
Field
Reset
R/W
15
Field
Reset
R/W
Address
Figure 17-21. FIFO Transmit FIFO Watermark Register (TFWR)
17-40
Uninitialized
Uninitialized
IPSBAR + 0x1124
Table 17-29. GALR Field Descriptions
Name
GADDR2 The GADDR2 register contains the lower 32 bits of the 64-bit
hash table used in the address recognition process for
receive frames with a multicast address. Bit 31 of GADDR2
contains hash index bit 31. Bit 0 of GADDR2 contains hash
index bit 0.
0000_0000_0000_0000
—
0000_0000_0000_0000
IPSBAR + 0x1144
MCF5282 User's Manual
GADDR2
R/W
GADDR2
R/W
Description
—
R/W
R/W
16
0
16
2 1 0
X_WMRK
MOTOROLA