Table of Contents
Advertisement
Entering stop mode will disable the SDRAMC including the
refresh counter. If SDRAM is used, then code is required to
insure proper entry and exit from stop mode. See
Section 7.3.2.5, "SDRAM Controller (SDRAMC)" for more
information.
7.3.1.5
Peripheral Shut Down
Most peripherals may be disabled by software in order to cease internal clock generation
and remain in a static state. Each peripheral has its own specific disabling sequence (refer
to each peripheral description for further details). A peripheral may be disabled at any time
and will remain disabled during any low-power mode of operation.
7.3.2
Peripheral Behavior in Low-Power Modes
7.3.2.1
ColdFire Core
The ColdFire core is disabled during any low-power mode. No recovery time is required
when exiting any low-power mode.
7.3.2.2
Static Random-Access Memory (SRAM)
SRAM is disabled during any low-power mode. No recovery time is required when exiting
any low-power mode.
7.3.2.3
Flash
The Flash module is in a low-power state if not being accessed. No recovery time is
required after exit from any low-power mode.
7.3.2.4
System Control Module (SCM)
The SCM's core Watchdog timer can bring the device out of all low-power modes except
stop mode. In stop mode, all clocks stop, and the core Watchdog does not operate.
When enabled, the core Watchdog can bring the device out of low-power mode in one of
two ways. If the core Watchdog reset/interrupt select (CSRI) bit is set, then a core Watchdog
timeout will cause a reset of the device. If the CSRI bit is cleared, then a core Watchdog
interrupt may be enabled and upon watchdog timeout, can bring the device out of
low-power mode. This system setup must meet the conditions specified in Section 7.3.1,
"Low-Power Modes" for the core Watchdog interrupt to bring the part out of low-power
mode.
MOTOROLA
NOTE
Chapter 7. Power Management
Functional Description
7-7
Advertisement
Table of Contents
