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Address
IPSBAR + 0x2BC
IPSBAR + 0x300
IPSBAR + 0x304
IPSBAR + 0x308
IPSBAR + 0x30C
IPSBAR + 0x310
IPSBAR + 0x340
IPSBAR + 0x344
IPSBAR + 0x348
IPSBAR + 0x34C
IPSBAR + 0x350
IPSBAR + 0x354
IPSBAR + 0x400
IPSBAR + 0x402
IPSBAR + 0x403
IPSBAR + 0x404
IPSBAR + 0x408
IPSBAR + 0x40C
IPSBAR + 0x440
IPSBAR + 0x442
IPSBAR + 0x443
IPSBAR + 0x444
IPSBAR + 0x448
IPSBAR + 0x44C
IPSBAR + 0x480
IPSBAR + 0x482
IPSBAR + 0x483
IPSBAR + 0x484
IPSBAR + 0x488
IPSBAR + 0x48C
MOTOROLA
Table A-3. Register Memory Map (Continued)
Name
(Read) Reserved
(Write) UART Output Port Bit Reset Command
Register 2
I
2
I
C Address Register
2
I
C Frequency Divider Register
2
I
C Control Register
2
I
C Status Register
2
I
C Data I/O Register
QSPI Registers
QSPI Mode Register
QSPI Delay Register
QSPI Wrap Register
QSPI Interrupt Register
QSPI Address Register
QSPI Data Register
DMA Timer Registers
DMA Timer Mode Register 0
DMA Timer Extended Mode Register 0
DMA Timer Event Register 0
DMA Timer Reference Register 0
DMA Timer Capture Register 0
DMA Timer Counter Register 0
DMA Timer Mode Register 1
DMA Timer Extended Mode Register 1
DMA Timer Event Register 1
DMA Timer Reference Register 1
DMA Timer Capture Register 1
DMA Timer Counter Register 1
DMA Timer Mode Register 2
DMA Timer Extended Mode Register 2
DMA Timer Event Register 2
DMA Timer Reference Register 2
DMA Timer Capture Register 2
DMA Timer Counter Register 2
Appendix A. Register Memory Map
3
2
C Registers
Mnemonic
Size
8
UIP02
8
I2ADR
8
I2FDR
8
I2CR
8
I2SR
8
I2DR
8
QMR
16
QDLYR
16
QWR
16
QIR
16
QAR
16
QDR
16
DTMR0
16
DTXMR0
8
DTER0
8
DTRR0
32
DTCR0
32
DTCN0
32
DTMR1
16
DTXMR1
8
DTER1
8
DTRR1
32
DTCR1
32
DTCN1
32
DTMR2
16
DTXMR2
8
DTER2
8
DTRR2
32
DTCR2
32
DTCN2
32
A-7
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