Table of Contents
Advertisement
The debug module has no hardware interlocks, so to prevent
spurious breakpoint triggers while the breakpoint registers are
being loaded, disable TDR (by clearing TDR[29,13])before
defining triggers.
A write to TDR clears the CSR trigger status bits, CSR[BSTAT].
31
30
29
Field
TRC
EBL
Reset
15
14
13
Field
LxT
EBL
Reset
R/W Write only. Accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the
BDM port using the
DRc[4–0]
Table 29-14 describes TDR fields.
Bits
Name
31–30
TRC
Trigger response control. Determines how the processor responds to a completed trigger condition. The
trigger response is always displayed on DDATA.
00 Display on DDATA only
01 Processor halt
10 Debug interrupt
11 Reserved
15–14
LxT
Level-x trigger. This is a Rev. B function only. The Level-x Trigger bit determines the logic operation for the
trigger between the PC_condition and the (Address_range & Data_condition) where the inclusion of a Data
condition is optional. The ColdFire debug architecture supports the creation of single or double-level triggers.
TDR[15]
0 Level-2 trigger = PC_condition & Address_range & Data_condition
1 Level-2 trigger = PC_condition | (Address_range & Data_condition)
TDR[14]
0 Level-1 trigger = PC_condition & Address_range & Data_condition
1 Level-1 trigger = PC_condition | (Address_range & Data_condition)
29/13
EBL
Enable breakpoint. Global enable for the breakpoint trigger. Setting TDR[EBL] enables a breakpoint trigger.
Clearing it disables all breakpoints at that level.
MOTOROLA
28
27
26
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
12
11
10
EDLW EDWL EDWU EDLL EDLM EDUM EDUU
command.
WDMREG
Figure 29-11. Trigger Definition Register (TDR)
Table 29-14. TDR Field Descriptions
Chapter 29. Debug Support
NOTE:
Second-Level Trigger
25
24
23
22
0000_0000_0000_0000
First-Level Trigger
9
8
7
6
0000_0000_0000_0000
0x07
Description
Programming Model
21
20
19
18
DI
EAI EAR EAL EPC
5
4
3
2
DI
EAI EAR EAL EPC
17
16
PCI
1
0
PCI
29-15
Advertisement
Table of Contents
