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Functional Description
reset the GPT counter. A channel 3 output compare can reset the GPT counter even if the
OC3/PAI pin is being used as the pulse accumulator input.
An output compare overrides the data direction bit of the output compare pin but does not
change the state of the data direction bit.
Writing to the PORTTn bit of an output compare pin does not affect the pin state. The value
written is stored in an internal latch. When the pin becomes available for general-purpose
output, the last value written to the bit appears at the pin.
20.6.4 Pulse Accumulator
The pulse accumulator (PA) is a 16-bit counter that can operate in two modes:
1. Event counter mode: counts edges of selected polarity on the pulse accumulator
input pin, PAI
2. Gated time accumulation mode: counts pulses from a divide-by-64 clock
The PA mode bit, PAMOD, selects the mode of operation.
The minimum pulse width for the PAI input is greater than two module clocks.
20.6.5 Event Counter Mode
Clearing the PAMOD bit configures the PA for event counter operation. An active edge on
the PAI pin increments the PA. The PA edge bit, PEDGE, selects falling edges or rising
edges to increment the PA.
An active edge on the PAI pin sets the PA input flag, PAIF. The PA input interrupt enable
bit, PAI, enables the PAIF flag to generate interrupt requests.
The PAI input and GPT channel 3 use the same pin. To use the
PAI input, disconnect it from the output logic by clearing the
channel 3 output mode and output level bits, OM3 and OL3.
Also clear the channel 3 output compare 3 mask bit, OC3M3.
The PA counter register, GPTPACNT, reflects the number of active input edges on the PAI
pin since the last reset.
The PA overflow flag, PAOVF, is set when the PA rolls over from 0xFFFF to 0x0000. The
PA overflow interrupt enable bit, PAOVI, enables the PAOVF flag to generate interrupt
requests.
The PA can operate in event counter mode even when the GPT
enable bit, GPTEN, is clear.
20-18
NOTE
NOTE
MCF5282 User's Manual
MOTOROLA
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