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If the MMFR register is written while frame generation is in progress, the frame contents
will be altered. Software should use the MII_STATUS register and/or the MII interrupt to
avoid writing to the MMFR register while frame generation is in progress.
17.5.4.7 MII Speed Control Register (MSCR)
The MSCR provides control of the MII clock (EMDC pin) frequency, allows a preamble
drop on the MII management frame, and provides observability (intended for
manufacturing test) of an internal counter used in generating the EMDC clock signal.
31
Field
Reset
R/W
15
Field
Reset
R/W
Address
Figure 17-10. MII Speed Control Register (MSCR)
Bits
31–8
7
DIS_PREAMBLE Asserting this bit will cause preamble (32 1's) not to be prepended
6–1
0
The MII_SPEED field must be programmed with a value to provide an EMDC frequency
of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification.
The MII_SPEED must be set to a non-zero value in order to source a read or write
management frame. After the management frame is complete the MSCR register may
optionally be set to zero to turn off the EMDC. The EMDC generated will have a 50% duty
cycle except when MII_SPEED is changed during operation (change will take effect
following either a rising or falling edge of EMDC).
MOTOROLA
0000_0000_0000_0000
—
0000_0000_0000_0000
Table 17-18. MSCR Field Descriptions
Name
—
Reserved, should be cleared.
to the MII management frame. The MII standard allows the preamble
to be dropped if the attached PHY device(s) does not require it.
MII_SPEED
MII_SPEED controls the frequency of the MII management interface
clock (EMDC) relative to the system clock. A value of 0 in this field
will "turn off" the EMDC and leave it in low voltage state. Any
non-zero value will result in the EMDC frequency of
1/(MII_SPEED*2) of the system clock frequency.
—
Reserved, should be cleared.
Chapter 17. Fast Ethernet Controller (FEC)
—
R/W
8
7
DIS_PREAMBLE
R/W
IPSBAR + 0x1044
Description
Programming Model
6
MII_SPEED
16
1
0
—
17-31
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