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Memory Map/Register Set
The additional MAC status register (MACSR) contains a 4-bit operational mode field and
condition flags. Operational mode bits control whether operands are signed or unsigned and
whether they are treated as integers or fractions. These bits also control the
overflow/saturation mode and the way in which rounding is performed. Negative, zero, and
multiple overflow condition flags are also provided.
3.4
Memory Map/Register Set
The EMAC provides the following program-visible registers:
• Four 32-bit accumulators (ACCn = ACC0, ACC1, ACC2, and ACC3)
• Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit
values for load and store operations (ACCext01 and ACCext23)
• One 16-bit mask register (MASK)
• One 32-bit MAC status register (MACSR) including four indicator bits signaling
product or accumulation overflow (one for each accumulator: PAV0–PAV3)
These registers are shown in Figure 3-6.
31
3.4.1
MAC Status Register (MACSR)
MACSR functionality is organized as follows:
• MACSR[11–8] contains one product/accumulation overflow flag per accumulator.
• MACSR[7–4] defines the operating configuration of the MAC unit.
• MACSR[3–0] contains indicator flags from the last MAC instruction execution.
Bit 31
Field
—
Reset
R/W
Table 3-1 describes MACSR fields.
3-6
0
MACSR
ACC0
ACC1
ACC2
ACC3
ACCext01
ACCext23
MASK
Figure 3-6. EMAC Register Set
12
11–8
Prod/acc overflow flags
PAVx
0000_0000_0000_0000_0000_0000_0000_0000
Figure 3-7. MAC Status Register (MACSR)
MCF5282 User's Manual
MAC status register
MAC accumulator 0
MAC accumulator 1
MAC accumulator 2
MAC accumulator 3
Extensions for ACC0 and ACC1
Extensions for ACC2 and ACC3
MAC mask register
7
6
5
Operational Mode
OMC S/U
F/I
R/W
4
3
2
1
0
Flags
R/T
N
Z
V
EV
MOTOROLA
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