Rsti; Block Diagram; Signals; Rsto - Motorola ColdFire MCF5281 User Manual

Block Diagram

28.2 Block Diagram
Figure 28-1 illustrates the reset controller and is explained in the following sections.

28.3 Signals

Table 28-1 provides a summary of the reset controller signal properties. The signals are
described in the following paragraphs.
Name

RSTI

RSTO

1
RSTI is always synchronized except when in low-power stop mode.
28.3.1 RSTI
Asserting the external RSTI for at least four rising CLKOUT edges causes the external reset
request to be recognized and latched.
28.3.2 RSTO
This active-low output signal is driven low when the internal reset controller module resets
the chip. When RSTO is active, the user can drive override options on the data bus.
28-2
RSTI
Pin
Power-On
Reset
Watchdog
Timer Timeout
PLL
Loss of Clock
PLL
Loss of Lock
Software
Reset
LVD
Detect
Figure 28-1. Reset Controller Block Diagram
Table 28-1. Reset Controller Signal Properties
Direction
I
O
MCF5282 User's Manual
RSTO
Pin
Reset
Controller
To Internal Resets
Input
Hysteresis
Y
—
Input
Synchronization
1
Y
—
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