Table of Contents
Advertisement
Bank 0
512 Kbyte
1 Mbyte
512 Kbyte
The DACRs should be programmed as shown in Figure 15-13.
31
Field
Setting
(hex)
F
15
14
13
Field
RE
—
Setting
(hex)
This configuration results in a value of DACR0 = 0xFF88_0300, as described in
Table 15-28. DACR1 initialization is not needed because there is only one block.
Subsequently, DACR1[RE,IMRS,IP] should be cleared; everything else is a don't care.
Bits
Name
31–18
BA
17–16
—
15
RE
14
—
13–12
CASL
11
—
10–8
CBM
7
—
6
IMRS
5–4
PS
MOTOROLA
SDRAM Component
Bank 1
512 Kbyte
1 Mbyte
512 Kbyte
Figure 15-12. SDRAM Configuration
F
12
11
10
CASL
—
CBM
0000_x011_x000_0000
Figure 15-13. DACR Register Configuration
Table 15-28. DACR Initialization Values
Setting
1111_1111_
Base address. So DACR0[31–16] = 0xFF88, placing the starting
1000_10
address of the SDRAM accessible memory at 0xFF88_0000.
Reserved. Don't care.
0
Keeps auto-refresh disabled because registers are being set up at this
time.
Reserved. Don't care.
00
Indicates a delay of data 1 cycle after SCAS is asserted
Reserved. Don't care.
011
Command bit is pin 20 and bank selects are 21 and up.
Reserved. Don't care.
0
Indicates
00
32-bit port.
Chapter 15. Synchronous DRAM Controller Module
Bank 2
512 Kbyte
1 Mbyte
512 Kbyte
BA
1111_1111_1000_10xx
8
8
7
6
—
IMRS
0300
Description
command has not been initiated.
MRS
SDRAM Example
Accessible
Memory
Bank 3
512 Kbyte
1 Mbyte
512 Kbyte
18
8
5
4
3
2
PS
IP
17
16
—
1
0
—
15-21
Advertisement
Table of Contents
