Flexcan Control Register 1 (Canctrl1); Canctrl0 Field Descriptions; Transmit Pin Configuration - Motorola ColdFire MCF5281 User Manual

Bits Name
Bus off interrupt mask. The BOFF MASK bit provides a mask for the bus off interrupt.
7 BOFFMSK 0 Bus off interrupt disabled.
1 Bus off interrupt enabled.
Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt.
6 ERRMSK 0 Error interrupt disabled.
1 Error interrupt enabled.
5–3 — Reserved
Receive pin configuration control. This bit determines the polarity of the CANRX pin.
2 RXMODE 0 A logical '0' is interpreted as a dominant bit; a logical '1' is interpreted as a recessive bit.
1 A logical '1' is interpreted as a dominant bit; a logical '0' is interpreted as a recessive bit.
Transmit pin configuration control. This bit field controls the configuration of the CANTX pin. See
1–0 TXMODE
Table 25-10.
TXMODE[1:0]
00
01
1X
1
Full CMOS drive indicates that both dominant and recessive levels are driven by the chip.
2
Open drain drive indicates that only a dominant level is driven by the chip. During a recessive
level, the CANTX pin is disabled (three stated), and the electrical level is achieved by external
pull-up/pull-down devices. The assertion of both Tx mode bits causes the polarity inversion to
be cancelled (open drain mode forces the polarity to be positive).

25.5.3 FlexCAN Control Register 1 (CANCTRL1)

7
Field SAMP
Reset
R/W
Address
Figure 25-8. FlexCAN Control Register 1 (CANCTRL1)
Table 25-11 describes the CANCTRL1 fields.
MOTOROLA
Table 25-9. CANCTRL0 Field Descriptions
Table 25-10. Transmit Pin Configuration

Transmit Pin Configuration

1
Full CMOS ; positive polarity (CANTX= 0 is a dominant level)
1
Full CMOS ; negative polarity (CANTX = 1 is a dominant level)
2
Open drain ; positive polarity
6 5
— TSYNC
IPSBAR + 0x1C_0007
Chapter 25. FlexCAN
Description
4 3
LBUF LOM
0000_0000
R/W
Programmer's Model
2 1 0
PROPSEG
25-23