Configuration/Status Register (Csr); Ablr Field Description; Abhr Field Description - Motorola ColdFire MCF5281 User Manual

Programming Model
Table 29-6 describes ABLR fields.
Bits Name
31–0 Address Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range.
Breakpoints for specific addresses are programmed into ABLR.
Table 29-7 describes ABHR fields.
Bits Name
31–0 Address High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.

29.4.4 Configuration/Status Register (CSR)

The CSR defines the debug configuration for the processor and memory subsystem and
contains status information from the breakpoint logic. CSR is write-only from the
programming model. It can be read from and written to through the BDM port. CSR is
accessible in supervisor mode as debug control register 0x00 using the WDEBUG
instruction and through the BDM port using the
31
Field BSTAT
Reset
1
R/W
15 14
Field MAP TRC EMU
Reset
R/W R/W R/W R/W
DRc[4–0]
29-10
Table 29-6. ABLR Field Description
Table 29-7. ABHR Field Description
28 27 26
FOF TRG HAL
R
13 12 11 10
DDC UHE
R/W R/W
Figure 29-7. Configuration/Status Register (CSR)
MCF5282 User's Manual
Description
Description
and
RDMREG
25 24 23
BKPT HRL
T
0000_0000_0000_0000
9 8 7 6
BTB — NPL
0000_0000_0000_0000
R/W R R/W
0000_0000_0000_0000
commands.
WDMREG
20 19
—
—
5 4 3
IPI SSM —
R/W R/W —
MOTOROLA
17 16
IPW
R/W
0