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Programming Model
Table 17-21. RCR Field Descriptions (continued)
Bits
1
0
17.5.4.10 Transmit Control Register (TCR)
The TCR is read/write and is written by the user to configure the transmit block. This
register is cleared at system reset. Bits 2 and 1 should be modified only when
ECR[ETHER_EN] = 0.
31
Field
Reset
R/W
15
Field
Reset
R/W
Address
Figure 17-13. Transmit Control Register (TCR)
17-34
Name
DRT
Disable receive on transmit.
0 Receive path operates independently of transmit (use for
full duplex or to monitor transmit activity in half duplex
mode).
1 Disable reception of frames while transmitting (normally
used for half duplex mode).
LOOP
Internal loopback. If set, transmitted frames are looped back
internal to the device and the transmit output signals are not
asserted. The system clock is substituted for the ETXCLK
when LOOP is asserted. DRT must be set to zero when
asserting LOOP.
0000_0000_0000_0000
—
0000_0000_0000_0000
R/W
IPSBAR + 0x10C4
MCF5282 User's Manual
Description
—
R/W
5
4
3
RFC_PAUSE TFC_PAUSE
R
16
2
1
0
FDEN
HBC GTS
R/W
MOTOROLA
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