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Processor Register Description
The processor core is comprised of two separate pipelines that are decoupled by an
instruction buffer.
The Instruction Fetch Pipeline (IFP) is a two-stage pipeline for prefetching instructions.
The prefetched instruction stream is then gated into the two-stage Operand Execution
Pipeline (OEP), which decodes the instruction, fetches the required operands and then
executes the required function. Since the IFP and OEP pipelines are decoupled by an
instruction buffer which serves as a FIFO queue, the IFP is able to prefetch instructions in
advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.
The Instruction Fetch Pipeline consists of two stages with an instruction buffer stage:
• Instruction Address Generation (IAG Cycle)
• Instruction Fetch Cycle (IC Cycle)
• Instruction Buffer (IB Cycle)
When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the
Operand Execution Pipeline. If the buffer is not empty, the IFP stores the contents of the
fetch cycle in the FIFO queue until it is required by the OEP. In the Version 2
implementation, the instruction buffer contains three 32-bit longwords of storage.
The Operand Execution Pipeline is implemented in a two-stage pipeline featuring a
traditional RISC datapath with a dual-read-ported register file (RGF) feeding an
arithmetic/logic unit. In this design, the pipeline stages have multiple functions:
• Decode & Select/Operand Cycle (DSOC Cycle)
• Address Generation/Execute Cycle (AGEX Cycle)
2.2
Processor Register Description
The following paragraphs describe the processor registers in the user and supervisor
programming models. The appropriate programming model is selected based on the
privilege level (user mode or supervisor mode) of the processor as defined by the S bit of
the status register (SR).
2.2.1
User Programming Model
Figure 2-2 illustrates the user programming model. The model is the same as the M68000
family microprocessors, consisting of the following registers:
• 16 general-purpose 32-bit registers (D0–D7, A0–A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
2-2
MCF5282 User's Manual
MOTOROLA
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