Begin Execution Of Taken Branch (Pst = 0X5) - Motorola ColdFire MCF5281 User Manual

Real-Time Trace Support
PST[3:0]
Hex Binary
0x7 0111 Begin execution of return from exception (RTE) instruction.
0x8– 1000–1 Indicates the number of bytes to be displayed on the DDATA port on subsequent processor clock cycles. The
0xB 011 value is driven onto the PST port one CLKOUT cycle before the data is displayed on DDATA.
0x8 Begin 1-byte transfer on DDATA.
0x9 Begin 2-byte transfer on DDATA.
0xA Begin 3-byte transfer on DDATA.
0xB Begin 4-byte transfer on DDATA.
0xC 1100 Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace) generate a
different encoding, as described below. Because the 0xC encoding defines a multiple-cycle mode, PST outputs
are driven with 0xC until exception processing completes.
0xD 1101 Entry into emulator mode. Displayed during emulation mode (debug interrupt or optionally trace). Because this
encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception processing completes.
0xE 1110 Processor is stopped. Appears in multiple-cycle format when the MCF5282 executes a STOP instruction. The
ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the stopped
mode is exited
0xF 1111 Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display 0xF until the
processor is restarted or reset. (see Section 29.5.1, "CPU Halt")

29.3.1 Begin Execution of Taken Branch (PST = 0x5)

PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may
be displayed on DDATA depending on the CSR settings. CSR also controls the number of
address bytes displayed, which is indicated by the PST marker value immediately
preceding the DDATA nibble that begins the data output.
Bytes are displayed in least-to-most-significant order. The processor captures only those
target addresses associated with taken branches which use a variant addressing mode, that
is, RTE and RTS instructions, JMP and JSR instructions using address register indirect or
indexed addressing modes, and all exception vectors.
The simplest example of a branch instruction using a variant address is the compiled code
for a C language case statement. Typically, the evaluation of this statement uses the variable
of an expression as an index into a table of offsets, where each offset points to a unique case
within the structure. For such change-of-flow operations, the MCF5282 uses the debug pins
to output the following sequence of information on successive processor clock cycles:
1. Use PST (0x5) to identify that a taken branch was executed.
2. Using the PST pins, optionally signal the target address to be displayed sequentially
on the DDATA pins. Encodings 0x9–0xB identify the number of bytes displayed.
3. The new target address is optionally available on subsequent cycles using the
DDATA port. The number of bytes of the target address displayed on this port is
configurable (2, 3, or 4 bytes).
29-4
Table 29-2. Processor Status Encoding (continued)
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MCF5282 User's Manual
Definition
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