Interrupt Flag Register (Iflag); Imask Field Descriptions; Iflag Field Descriptions - Motorola ColdFire MCF5281 User Manual

Bits Name
15–0 BUFnM IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which buffers will
generate interrupts after successful transmission/reception.
0 The interrupt for the corresponding buffer is disabled.
1 The interrupt for the corresponding buffer is enabled.

25.5.10 Interrupt Flag Register (IFLAG)

IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception
sets the corresponding IFLAG bit and, if the corresponding IMASK bit is set, will generate
an interrupt.
This register contains two 8-bit fields: bits 15-8 (IFLAG_H) and bits 7-0 (IFLAG_L). The
register can be accessed by the master as a 16-bit register, or each byte can be accessed
individually using an 8-bit (byte) access cycle.
15
Field BUF15I
Reset
R/W
7
Field BUF7I
Reset
R/W
Address
Table 25-19 describes the IFLAG fields.
Bits Name
15–0 BUFnI IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets the
corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request will be
generated.
To clear an interrupt flag, first read the flag as a one, and then write it as a zero. Should a new flag
setting event occur between the time that the CPU reads the flag as a one and writes the flag as a
zero, the flag is not cleared. This register can be written to zeros only.
0 The interrupt for the corresponding buffer is disabled.
1 The interrupt for the corresponding buffer is enabled.
MOTOROLA
Table 25-18. IMASK Field Descriptions
14 13
BUF14I BUF13I
6 5
BUF6I BUF5I
Figure 25-15. Interrupt Flag Register (IFLAG)
Table 25-19. IFLAG Field Descriptions
Chapter 25. FlexCAN
Description
12 11
BUF1I BUF11I
0000_0000
R/w
4 3
BUF4I BUF3I
0000_0000
R/W
IPSBAR + 0x1C_0024
Description
Programmer's Model
10 9
BUF10I BUF9I
BUF2I BUF1I
8
BUF8I
0
BUF0I
25-31