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Address
IPSBAR + 0x1D0
IPSBAR + 0x200
IPSBAR + 0x204
IPSBAR + 0x208
IPSBAR + 0x20C
IPSBAR + 0x210
IPSBAR + 0x214
IPSBAR + 0x218
IPSBAR + 0x21C
IPSBAR + 0x234
IPSBAR + 0x238
IPSBAR + 0x23C
IPSBAR + 0x240
IPSBAR + 0x244
IPSBAR + 0x248
IPSBAR + 0x24C
IPSBAR + 0x250
MOTOROLA
Table A-3. Register Memory Map (Continued)
Name
DMA Status Register 3
UART Registers
UART Mode Register 0
(Read) UART Status Register 0
(Write) UART Clock Select Register 0
(Read) Reserved
(Write) UART Command Register 0
(Read) UART Receive Buffer 0
(Write) UART Transmit Buffer 0
(Read) UART Input Port Change Register 0
(Write) UART Auxiliary Control Register 0
(Read) UART Interrupt Status Register 0
(Write) UART Interrupt Mask Register 0
(Read) Reserved
UART Baud Rate Generator Register 10
(Read) Reserved
UART Baud Rate Generator Register 20
(Read) UART Input Port Register 0
(Write) Reserved
(Read) Reserved
(Write) UART Output Port Bit Set Command
Register 0
(Read) Reserved
(Write) UART Output Port Bit Reset Command
Register 0
UART Mode Registers 1
(Read) UART Status Register 1
(Write) UART Clock Select Register 1
(Read) Reserved
(Write) UART Command Register 1
(UART/Read) UART Receive Buffer 1
(UART/Write) UART Transmit Buffer 1
(Read) UART Input Port Change Register 1
(Write) UART Auxiliary Control Register 1
Appendix A. Register Memory Map
Mnemonic
DSR3
2
UMR10,
UMR20
USR0
1
UCSR0
UCR0
URB0
UTB0
UIPCR0
1
UACR0
UISR0
UIMR0
3
UBG10
3
UBG20
UIP0
3
3
UOP10
3
UIP00
2
UMR11,
UMR21
USR1
1
UCSR1
3
UCR1
URB1
UTB1
UIPCR1
1
UACR1
Size
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
A-5
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