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MCF5282 External Signals
These pins can also be configured as GPIO PEL4.
14.2.6.13 Receive Data 1–3 (ERXD[3:1])
These pins contain the Ethernet input data transferred from the PHY to the media-access
controller when ERXDV is asserted in MII mode operation.
These pins can also be configured as GPIO PEL[3:1].
14.2.6.14 Receive Error (ERXER)
ERXER is an input signal which when asserted along with ERXDV signals that the PHY
has detected an error in the current frame. When ERXDV is not asserted ERXER has no
effect, and applies to MII mode operation.
These pins can also be configured as GPIO PEL0.
14.2.7 Queued Serial Peripheral Interface (QSPI) Signals
14.2.7.1 QSPI Synchronous Serial Output (QSPI_DOUT)
The QSPI_DOUT output provides the serial data from the QSPI and can be programmed to
be driven on the rising or falling edge of QSPICLK. Each byte is sent msb first.
This pin can also be configured as GPIO PQS0.
14.2.7.2 QSPI Synchronous Serial Data Input (QSPI_DIN)
The QSPI_DIN input provides the serial data to the QSPI and can be programmed to be
sampled on the rising or falling edge of QSPICLK. Each byte is written to RAM lsb first.
This pin can also be configured as GPIO PQS1.
14.2.7.3 QSPI Serial Clock (QSPI_CLK)
The QSPI serial clock (QSPI_CLK) provides the serial clock from the QSPI. The polarity
and phase of QSPI_CLK are programmable. The output frequency is programmed
according to the following formula, in which n can be any value between 2 and 255:
QSPI_CLK = CLKOUT/(2n).
This pin can also be configured as GPIO PQS2.
14.2.7.4 QSPI Chip Selects (QSPI_CS[3:0])
The synchronous peripheral chip selects (QSPI_CS[3:0]) outputs provide QSPI peripheral
chip selects that can be programmed to be active high or low.
This pin can also be configured as GPIO PQS[6:3].
MOTOROLA
Chapter 14. Signal Descriptions
14-25
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