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Digital Control Subsystem
System Clock
Divide
by 2
Input Sample Time
from CCW
Queue 1 and Queue 2 Timer
Mode Rate Selection
A change in the prescaler value while a conversion is in
progress is likely to corrupt the result. Therefore, any prescaler
write operation should be done only when both queues are in
the disabled modes.
To accommodate the wide range of the system clock frequency, QCLK is generated by a
programmable prescaler which divides the system clock. To allow the A/D conversion time
to be maximized across the spectrum of system clock frequencies, the QADC prescaler
permits the QCLK frequency to be software selectable. The frequency of QCLK is set with
the QPR field in QACR0.
27.8.9 Periodic/Interval Timer
The QADC periodic/interval timer can be used to generate trigger events at a
programmable interval, initiating execution of queue 1 and/or queue 2. The
periodic/interval timer stays reset under these conditions:
• Both queue 1 and queue 2 are programmed to any mode which does not use the
periodic/interval timer.
• System reset is asserted.
• Stop mode is enabled.
• Debug mode is enabled.
27-58
QPR[6:0]
Prescaler
ATD Converter
2
State Machine
Binary Counter
7
8
9
10
11
2
2
2
2
2
8
Periodic Timer/Interval Timer
Figure 27-42. QADC Clock Subsystem Functions
CAUTION
MCF5282 User's Manual
12
13
14
15
16
17
2
2
2
2
2
2
Select
SAR Control
SAR
10
Periodic/Interval Trigger
2
Event for Q1 and Q2
MOTOROLA
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