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Chip Select Registers
Table 12-7. CSMRn Field Descriptions (continued)
Bits
Name
5–1
C/I, SC,
Address space mask bits. These bits determine whether the specified accesses can occur to the
SD, UC,
address space defined by the BAM for this chip select.
UD
C/I
CPU space and interrupt acknowledge cycle mask
SC Supervisor code address space mask
SD Supervisor data address space mask
UC User code address space mask
UD User data address space mask
0 The address space assigned to this chip select is available to the specified access type.
1 The address space assigned to this chip select is not available (masked) to the specified access
type. If this address space is accessed, chip select is not activated and a regular external bus
cycle occurs.
Note that if AM = 0, SC, SD, UC, and UD are ignored in the chip select decode on DMA access.
0
V
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are valid.
Programmed chip selects do not assert until V is set (except for CS0, which acts as the global chip
select). Reset clears each CSMRn[V].
0 Chip select invalid
1 Chip select valid
12.4.1.3 Chip Select Control Registers (CSCR0–CSCR6)
Each CSCR, shown in Figure 12-4, controls the auto-acknowledge, port size, burst
capability, and activation of each chip select. Note that to support the external boot chip
select, CS0, the CSCR0 reset values differ from the other CSCRs. CS0 allows address
decoding for boot ROM before system initialization.
15
Field
Reset: CSCR0
Reset: Other CSCRs
R/W
Address
Figure 12-4. Chip Select Control Registers (CSCRn)
Table 12-8 describes CSCRn fields.
12-8
14
13
—
WS
—
11_11
0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3);
0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6)
MCF5282 User's Manual
Description
10
9
8
7
6
—
AA PS1 PS0 BEM BSTR BSTW
—
1
D19 D18
Uninitialized
R/W
5
4
3
2
—
—
MOTOROLA
0
—
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