Table of Contents
Advertisement
Digital Control Subsystem
While the gate is open, queue 1 executes one time. Each CCW is read and the indicated
conversions are performed until an end-of-queue condition is encountered. When queue 1
completes, the QADC sets the completion flag (CF1) and clears the single-scan enable bit.
Set the single-scan enable bit again to allow another scan of queue 1 to be initiated during
the next open gate.
If the gate closes before queue 1 completes execution, the current CCW completes,
execution of queue 1 stops, the single-scan enable bit is cleared, and the PF1 bit is set. The
CWPQ1 field can be read to determine the last valid conversion in the queue. The
single-scan enable bit must be set again and the PF1 bit should be cleared before another
scan of queue 1 is initiated during the next open gate. The start of queue 1 is always the first
CCW in the CCW table.
Because the gate level is only sampled after each conversion during queue execution,
closing the gate for a period less than a conversion time interval does not guarantee the
closure will be captured.
27.8.6.4 Interval Timer Single-Scan Mode
Both queues can use the periodic/interval timer in a single-scan queue operating mode. The
7
17
timer interval can range from 2
to 2
QCLK cycles in binary multiples. When the interval
timer single-scan mode is selected and the single-scan enable bit is set in QACR1 or
QACR2, the timer begins counting. When the time interval elapses, an internal trigger
event is generated to start the queue and the QADC begins execution with the first CCW.
The QADC automatically performs the conversions in the queue until a pause or an
end-of-queue condition is encountered. When a pause occurs, queue execution stops until
the timer interval elapses again, and queue execution continues. When queue execution
reaches an end-of-queue situation, the single-scan enable bit is cleared. Set the single-scan
enable bit again to allow another scan of the queue to be initiated by the interval timer.
The interval timer generates a trigger event whenever the time interval elapses. The trigger
event may cause queue execution to continue following a pause or may be considered a
trigger overrun. Once queue execution is completed, the single-scan enable bit must be set
again to allow the timer to count again.
Normally, only one queue is enabled for interval timer single-scan mode, and the timer will
reset at the end-of-queue. However, if both queues are enabled for either single-scan or
continuous interval timer mode, the end-of-queue condition will not reset the timer while
the other queue is active. In this case, the timer will reset when both queues have reached
end-of-queue. See Section 27.8.9 for a definition of interval timer reset conditions.
The interval timer single-scan mode can be used in applications that need coherent results.
For example:
• When it is necessary that all samples are guaranteed to be taken during the same scan
of the analog signals
MOTOROLA
Chapter 27. Queued Analog-to-Digital Converter (QADC)
27-53
Advertisement
Table of Contents
