Burst Read Sdram Access - Motorola ColdFire MCF5281 User Manual

SDRAM Controller Operation
the port size of the associated SDRAM. The primary cycle of the transfer generates the
and or
ACTV READ
commands. As soon as the transfer completes, the
for the next access.
Note that in synchronous operation, burst mode and address incrementing during burst
cycles are controlled by the MCF5282 DRAM controller. Thus, instead of the SDRAM
enabling its internal burst incrementing capability, the MCF5282 controls this function.
This means that the burst function that is enabled in the mode register of SDRAMs must be
disabled when interfacing to the MCF5282.
Figure 15-6 shows a burst read operation. In this example, DACR[CASL] = 01 for an
SRAS-to-SCAS delay (t
CAS latency (SCAS assertion to data out), this value is also 2 system clock cycles. Notice
that s are executed until the last data is read. A
NOP
after the last data transfer.
CLKOUT
A[31:0]
SRAS
SCAS
DRAMW
D[31:0]
SDRAM_CS[0] or [1]
BS[3:0]
Figure 15-7 shows the burst write operation. In this example, DACR[CASL] = 01, which
creates an SRAS-to-SCAS delay (t
upon SCAS assertion and a burst write cycle completes two cycles sooner than a burst read
cycle with the same t
SDRAM cycle until the precharge-to-
15-14
commands; secondary cycles generate only
WRITE
) of 2 system clock cycles. Because t
RCD
Row Column Column
t = 2
RCD
ACTV NOP READ
Figure 15-6. Burst Read SDRAM Access
) of 2 system clock cycles. Note that data is available
RCD
The next bus cycle is initiated sooner, but cannot begin an
RCD.
ACTV
MCF5282 User's Manual
command is generated to prepare
PALL
command is executed one cycle
PALL
Column Column
t = 2
CASL
READ READ READ
delay completes.
or
READ WRITE
is equal to the read
RCD
t
EP
NOP NOP PALL
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